Preeti Ranjan Panda, Computer Science and Engineering, IIT Delhi

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This semester

Nothing recorded this semester.

Earlier

COL812
System Level Design and Modelling
3 (3-0-0) credits · Sem 2, 2025-26
unrated
COL8412
System Level Design and Modelling
3 (3-0-0) credits · Sem 2, 2025-26
unrated
COL215
Digital Logic & System Designrunning now
5 (3-0-4) credits · Sem 1, 2025-26, Sem 2, 2024-25, Sem 1, 2024-25, Sem 1, 2023-24, Sem 1, 2022-23
unrated
COL719
Synthesis of Digital Systems
4 (3-0-2) credits · Sem 2, 2024-25, Sem 2, 2023-24, Sem 2, 2022-23
unrated

Each course has its own page and discussion.

Doing a BTP, MTP, PhD, internship or RA position under Panda, scored on five separate axes.

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Mentorship5

1 · left yourself to itclosely guided · 10

Availability5

1 · weeks to get a replyresponds same day · 10

Freedom5

1 · told exactly what to dopicked my own direction · 10

Workload5

1 · lightpunishing · 10

Credit5

1 · contribution went unacknowledgedscrupulously fair on authorship · 10

These are deliberately not all “high is good”. Someone who wants heavy guidance and someone who wants total autonomy are looking for opposite ends of the Freedom axis. Answer honestly about what it was like; readers will judge fit.

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Areas listed by the department

Embedded SystemsHardware Accelerators for AI/MLComputer ..

Publications, via OpenAlex

28h-index

3463Citations

181Works

58i10

Topic clusters

Parallel Computing and Optimization TechniquesEmbedded Systems Design TechniquesLow-power high-performance VLSI designVLSI and FPGA Design TechniquesInterconnection Networks and Systems

Most recent

Application-Aware Memory Management for IPsec on Heterogeneous SoCs · IFIP advances in information and communication technology, 2026
Modeling Energy and Delay for ECC-Enabled Cache Architectures · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026
FARRE: Fairness Aware Request Response Arbitration in Shared Caches · ACM Transactions on Embedded Computing Systems, 2025
SHARP: SHARing-Aware Cache Writeback byPass · ACM Transactions on Embedded Computing Systems, 2025

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