Rakesh K. Palani, Electrical Engineering, IIT Delhi

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This semester

ELL304
Analog Electronicsrunning now
5.5 (3-1-3) credits · Slot F · TThF 11:00-12:00
unrated

Earlier

ELL304
Analog Electronicsrunning now
5.5 (3-1-3) credits · Sem 2, 2025-26, Sem 1, 2025-26
unrated
ELL731
Mixed Signal Circuit Design
3 (3-0-0) credits · Sem 2, 2025-26, Sem 2, 2023-24
unrated
ELL7314
VLSI Data Conversion Circuit Design
3 (3-0-0) credits · Sem 2, 2025-26
unrated
ELL7304
Analog Circuit Designrunning now
3 (3-0-0) credits · Sem 1, 2025-26
unrated
ELL735
Analog Integrated Circuitsrunning now
3 (3-0-0) credits · Sem 1, 2025-26
unrated
ELL832
Selected Topics in IEC-Irunning now
3 (3-0-0) credits · Sem 2, 2024-25
unrated
ELP101
Introduction to Electrical Engineering (Laboratory)
1 (0-0-2) credits · Sem 2, 2023-24, Sem 2, 2022-23
unrated
ELL202
Circuit Theory
4 (3-1-0) credits · Sem 1, 2023-24
unrated
ELL734
MOS VLSI designrunning now
3 (3-0-0) credits · Sem 1, 2022-23
unrated

Each course has its own page and discussion.

Doing a BTP, MTP, PhD, internship or RA position under Palani, scored on five separate axes.

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Mentorship5

1 · left yourself to itclosely guided · 10

Availability5

1 · weeks to get a replyresponds same day · 10

Freedom5

1 · told exactly what to dopicked my own direction · 10

Workload5

1 · lightpunishing · 10

Credit5

1 · contribution went unacknowledgedscrupulously fair on authorship · 10

These are deliberately not all “high is good”. Someone who wants heavy guidance and someone who wants total autonomy are looking for opposite ends of the Freedom axis. Answer honestly about what it was like; readers will judge fit.

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Areas listed by the department

Research Interests: Analog/RF Mixed Signal DesignData ConvertersLow power CircuitsFrequency Reference circuits

Publications, via OpenAlex

11h-index

319Citations

33Works

11i10

Topic clusters

Analog and Mixed-Signal Circuit DesignRadio Frequency Integrated Circuit DesignLow-power high-performance VLSI designDigital Filter Design and ImplementationAdvancements in PLL and VCO Technologies

Most recent

Architecture and Design of 1.6-GS/s Digital Frequency Up/Down Converter Based on Polyphase Filter Bank · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2026
Design and Analysis of Voltage Regulators for Retimer Latches in RF NRZ DACs · 2025
Sub-1 V, 3.14 PPM $/{ }^{\circ} \mathrm{C}$ Folded Bandgap Reference · Conference proceedings, 2025
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars · IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024 · 8 citations
Analysis and design of Chopperless 7 ppm/°C Bandgap Voltage Reference · IEEE International Symposium on Circuits and Systems proceedings, 2024 · 3 citations

Matched to Rakesh Kumar Palani on OpenAlex. Author matching is by name and institution and can be wrong for common names.

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